The present invention concerns an arithmetic and logic unit such as those which are utilized in microprocessors or other circuits for processing binary signals.
An arithmetic and logic unit is intended to receive two binary numbers of several digits and to carry out on these numbers simple arithmetic type operations (the addition or subtraction of two numbers) or logic type operations (complementation, OR function, etc.). It is constituted by a succession of switching cells each receiving a binary number or bit of one of the numbers to be processed and a binary number or bit of the other number; control conductors, for example eight in number, control the switching cell according to the arithmetic or logic function to be carried out, in such a way as to switch onto the output of each cell one or other of the bits, or their complement, or again a "zero" bit or "one" bit, according to the function to be carried out.
A constitution example of an arithmetic and logic unit (ALU) is represented in FIG. 1.
The ALU comprises a succession of n cells C.sub.o to C.sub.n-1 in order to process numbers A and B each of n bits, a.sub.o to a.sub.n-1 and b.sub.o to b.sub.n-1, the more significant bits a.sub.n-1 and b.sub.n-1' processed in the cell of rank n-1, being sign bits of numbers A and B.
The bits of rank i, a.sub.i and b.sub.i respectively, are applied to the input of cell C.sub.i of rank i.
Each cell C.sub.i comprises two switching elements K.sub.i and P.sub.i each receiving bit a.sub.i and bit b.sub.i and eventually their complements a.sub.i and b.sub.i, if these complements are not generated inside the elements themselves.
Elements K.sub.i and P.sub.i of the various cells are all controlled simultaneously by common control conductors, for example, eight in number, grouped together in a control bus designated by reference cd. The state of the signals on the various control conductors defines the arithmetic or logic function carried out by the ALU and this function becomes apparent by the appearance at the output of each switching element of a signal that can be a.sub.i or b.sub.i or a.sub.i or b.sub.i or 0 or 1.
Each cell C.sub.i comprises, apart from the inputs for numbers a.sub.i and b.sub.i, a carrying input designated by r.sub.i-1, connected to the carrying output, also designated by r.sub.i-1, of the cell of the immediately preceding rank C.sub.i-1.
Cell C.sub.i comprises furthermore a result output S.sub.i and q carrying output r.sub.i adapted to be connected to the input of the cell of the following rank C.sub.i+1.
In the example represented, the output of switching element K.sub.i controls a field effect transistor T1.sub.i connected between carrying output r.sub.i and a mass (logic level 0). Switching output element P.sub.i is connected, on the one hand, to the control grid of a transistor T2.sub.i connected between carrying input (r.sub.i-1) and carrying output (r.sub.i). Furthermore, switching output element P.sub.i is connected to an input of an exclusive OR gate EO.sub.i, the other input of which is connected to carrying input r.sub.i-1 and the output of which constitutes result output S.sub.i of cell C.sub.i.
Furthermore, a transistor T3.sub.i, connected between carrying output r.sub.i and a power supply V.sub.p, acting to ensure a precharge of the circuit in a first operating phase of the ALU during which this transistor is rendered conductor.
Generally, it is required to know, when the ALU operates as an adder or a subtractor, if the addition or subtraction capacity of the ALU has not overflowed. Indeed, input numbers A and B are numbers bearing a sign the most significant bit of which (a.sub.n-1 or b.sub.n-1) represents the sign, positive if it is zero, negative if it is equal to 1; the output of the ALU is equally a number bearing a sign of which the most significant bit s.sub.n-1 (output of cell C.sub.n-1 of the most significant rank) represents the sign of the addition or subtraction result. It is possible that the addition of two positive numbers gives a positive result equal to or higher than 2.sup.n-1, in which case sign bit s.sub.n-1 will become equal to 1, which would then be interpreted as a negative result; if the capacity of the ALU is exceeded, it is known as positive overflow. It is also possible that the addition of two negative numbers give a negative result lower than -2.sup.n-1, in which case sign bit s.sub.n-1 will become equal to 0, and the result supplied by the ALU, interpreted as a positive number, will obviously be incorrect: there is again capacity overflow, that will be known as negative overflow.
Furthermore, positive overflow is possible in the case of A-B subtraction where A is positive and B is negative and a negative overflow is possible in the case of A-B subtraction where A is negative and B positive.
The arithmetic and logic units are thus generally provided with an overflow test circuit, represented under general reference TD, which elaborates a positive overflow signal and a negative overglow signal dn.
These signals are utilized by the processor or microprocessor, the ALU of which forms the body; for example, these signals are registered at specific positions of a state register comprising furthermore other indications on the state of the processor.
In practice, if the detail of the overflow test circuit, it will be observed that it is usually elaborated from following comments a.sub.n-1, b.sub.n-1 and s.sub.n-1 being the sign bits of numbers A and B and of the result S of the addition or the subtraction A and B:
1. in the addition mode
(a) if A and B are positive (a.sub.n-1 =b.sub.n-1 =0) and if S is negative (s.sub.n-1 =1), there is positive overflow: dp=1; it is possible to write logic equation: EQU dp=a.sub.n-1 b.sub.n-1 s.sub.n-1 ( 1) PA1 (b) if A and B are negative (a.sub.n-1 =b.sub.n-1 =1) and if S is positive (s.sub.n-1 =0), there is negative overflow: dn=1; it is possible to write the logic equation: EQU dn=a.sub.n-1 b.sub.n-1 s.sub.n-1 ( 2) PA1 (a) if A is positive and B negative (a.sub.n-1 =0; b.sub.n-1 =1) and if S is negative (s.sub.n-1 =1), there is positive overflow: dp=1; it is possible to write the logic equation: EQU dp=a.sub.n-1 b.sub.n-1 s.sub.n-1 ( 3) PA1 (b) if A is negative and B positive (a.sub.n-1 =1; b.sub.n-1 =0) and if S is positive (s.sub.n-1 =0), there is negative overflow dn=1; it is possible to write the logic equation: EQU dn=a.sub.n-1 b.sub.n-1 s.sub.n-1 ( 4) PA1 sign bit a.sub.n-1 of A PA1 sign bit b.sub.n-1 of B PA1 sign bit s.sub.n-1 of result S PA1 an indination on the work mode, ALU addition or subtraction.
2. A-B subtraction mode
It will be noted that the logic equation (1) and (3) are not identical, in the same way as equations (2) and (4). It is thus in priority necessary to establish overflow signals separately for the case where the ALU carries out an addition, and for the case where it carries out a subtraction. Test circuit TD must therefore receive:
This latter indication originates from one or several control bus conductors cd of the ALU.
Other than the fact that it is necessary to foresee bringing to the test signals circuit of the control bus of the ALU, it is thus necessary to provide a logic circuit of several gate levels: a first level of inverters in order to realize the complements a.sub.n-1, b.sub.n-1, s.sub.n-1, four gates with three inputs at least to realize the various products appearing in logic equations (1) and (4) and gates to select adequate products in function of the control bus state cd.
In order to reduce the number of gates necessary and above all the number of successive stages of gates in order to accelerate the obtention of overflow date, the present invention proposes an arithmetic and logic unit having an overflow test circuit that possesses three inputs respectively connected to the carrying input of the cell of the highest rank of the arithmetic and logic unit, at the carrying output of this cell, and finally the result output of this cell.
This circuit essentially comprises, other than the inverters in order to establish the complement of the signals applied to these inputs, a single gate of three inputs for each overflow date to be established (i.e. two gates if positive overflow date and negative overflow date is required).